Semiconductor devices, such as integrated circuit (IC) devices, are typically fabricated in the form of small, thin, and thus fragile, dies or chips which are electrically connected to a lead frame or other mounting by means of a plurality of leads extending therefrom and attached to very fine and fragile wires, and then protected from physical damage, environmentally-induced degradation, etc., by means of an encapsulant material which surrounds the die or chip and associated lead frame or other type mounting. According to conventional large-scale manufacturing technology, a plurality of individual dies or chips are physically secured, and electrically connected, to a common substrate, e.g., a copper (Cu) or Cu alloy-based substrate in the form of an elongated strip, and then encapsulated, as by molding, within a layer of encapsulant material, typically an epoxy resin-based material. The common substrate can be in the form of a narrow strip having a single row of spaced-apart encapsulated dies or chips mounted on the surface thereof or in a wider form for mounting thereon a two-dimensional array of encapsulated dies or chips arranged in rows and columns. In either instance, a plurality of discrete device packages are obtained from the encapsulated array by segmenting the substrate in the spaces between adjacent dies or chips.
In recent years, electronic device packages of relatively low height profile have been developed, which in turn include a relatively thin, thus easily deformable substrate, e.g., of Cu or Cu-based alloy. Such packages are referred to in the art as "TSOP"s. the acronym for thin, small outline packages. Such devices, or packages, having a low vertical profile, occupy a minimum of height on the substrate, and further are capable of being surface mounted to respective circuitry on the substrate surface, e.g., conductor pads, by means of conventional, e.g., soldering, techniques. Thus, TSOP packages are able to provide a desired electrical or electronic function while assuring a compact, low profile which affords a substantial savings in space for the final product utilizing same.
According to conventional methodology for large-scale manufacture of such TSOPs, a plurality of semiconductor IC dies or chips, along with their respective lead frames, are mounted in spaced-apart fashion to form an array on the surface of a thin substrate and electrically connected to respective circuitry thereon, the substrate typically comprised of a Cu or Cu alloy-based thin sheet or foil about 0.120 to about 0.135 mm thick. The resultant array is placed in a suitably configured, heated mold for encapsulating each die or chip in a layer of molding or encapsulant material, e.g., an epoxy resin-based material. Molding for encapsulation utilizing conventionally employed epoxy resin-based materials is typically performed at a temperature of about 175+/-5.degree. C. for about 60 to about sec. Subsequent to molding, a plurality of the encapsulated, strip-shaped arrays are vertically stacked and loaded into magazines for insertion into ovens for performing post-mold curing, typically at about 175.degree. C. for about 5 hrs. for conventional epoxy resin-based molding materials. After completion of post-mold curing, the magazines are removed from the ovens and the post-mold cured, encapsulated arrays permitted to cool down in the ambient air to room temperature (typically within about 30-45 min.).
However, when performing the above-described conventional molding for device encapsulation, it has been found necessary to place heavy metal (e.g., lead, Pb) bars on top of the stack of encapsulated arrays loaded into each magazine prior to performing the post-mold curing process, in order to avoid undesirable chip and/or substrate warpage which otherwise results from the post-mold curing process, which warpage has been correlated with unacceptable loss of electrical lead co-planarity. Disadvantageously, however, the placement of the heavy metal bars to the tops of the encapsulated arrays loaded into the magazines prior to performing the post-mold curing is conducted manually, and therefore is a time-consuming process which runs counter to the requirements of economically viable, automated, mass-production techniques and methodologies.
Accordingly, there exists a need for improved methodology for reliable, high quality manufacture of arrays of encapsulated semiconductor IC devices and discrete device packages therefrom, such as TSOPs, which methodology avoids the above-described drawbacks and disadvantages attendant upon fabrication according to conventional encapsulation processing, including, inter alia, loss of electrical lead co-planarity and time consuming placement and removal of heavy metal bars used for prevention of strip warpage upon post-mold curing. Moreover, there exists a need for improved encapsulation methodology for making devices such as TSOPs which is fully compatible with all aspects, including cost and throughput requirements, of mass manufacturing techniques.
The present invention, wherein the molding material selected for encapsulation of the IC dies or chips forming part of the TSOP devices exhibits, inter alia, a reduced coefficient of thermal expansion which provides good compatibility with the thermal expansion characteristics of the other components of the package, e.g., the IC chip, lead frame, and substrate, and an increased flexural modulus at both high and low temperatures which places less deformation-inducing forces on the other components of the package, effectively addresses and solves the above-described problems and drawbacks of the conventional methodology. According to the present invention, the drawbacks and disadvantages associated with the use of conventional encapsulant materials which produce molding material-induced stresses tending to cause warpage of the thin, e.g., Cu or Cu alloy-based substrates utilized in forming the TSOPs, are substantially eliminated, or at least minimized, thereby effectively preventing loss of lead co-planarity without requiring time-consuming, manual placement of heavy metal bars on top of the array stack loaded into magazines prior to performing post-mold curing. Further, the methodology provided by the instant invention enjoys diverse utility in the manufacture of all manner of encapsulated device arrays and discrete device packages obtained therefrom.